CV Lattes
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Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Instituto de Geociências e Ciências Exatas (IGCE) (Institutional affiliation from the last research proposal) Birthplace: Brazil
He is an Associate Professor (MS-5.3) at the Institute of Geosciences and Exact Sciences (IGCE), São Paulo State University (UNESP), in Rio Claro. His research focuses on Parallel Systems, with an emphasis on infrastructure and hardwaresoftware interaction. He worked with the Microsoft Research group in 2010 (holding a registered patent) under the leadership of Prof. James Larus; he was a visiting professor at Bangor University (2016, UK) and the University of Nottingham (2019, China), and has collaborated with researchers from other universities, including the University of Alberta and the University of Washington. He completed a postdoctoral fellowship at Instituto Superior Técnico of Lisbon / INESC-ID between 2019 and 2020, where he contributed to the development of transactional support for persistent systems, resulting in significant publications in ACM Computing Surveys, USENIX FAST, and ACM EuroSys. He has actively participated in national initiatives to promote High-Performance Computing, having served as the coordinator of the São Paulo State Regional School of High Performance Computing (ERAD-SP) in 2024, and as president of the São Paulo Regional Council for High Performance Computing (CRAD-SP) from 2023 to 2025. He is a regular member of the program committee of the Symposium on High Performance Computing Systems (SSCAD), where he also served as Program Committee Chair in 2022. (Source: Lattes Curriculum)
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Multicore machines are ubiquitous nowadays and the tendency is for semiconductor companies to keep adding more and more cores into their new microprocessors. Unfortunately, support for programming these highly parallel machines have not kept pace and we are left with underutilized computer systems. The big challenge facing the industry today is how to ease the life of programmers in writi…
Microarchitectural limitations and high energy dissipation have forced the semiconductor industry to shift from single-core processors to multicores. This new approach allows the transistor growth foresaw by Moore's law to continue but, instead of increasing the clock frequency and exploiting instruction level parallelism, more cores are being integrated into a single die. This shift has …
In this project we seek to investigate the tradeoffs between programming and performance in the main PM systems. This investigation will seek to shed some light on issues such as: in what scenarios does using a more performance-efficient system (such as PMDK)pay off, even if the programming cost is much higher? Is it possible to keep a high-level programming abstraction while optimizing t…
In this study we aim to investigate how current memory allocators for PM perform in a NUMA environment. In a previous study, we identified that indeed some types of allocators did not perform well in a NUMA environment. Therefore, in this work we seek to identify the main causes and provide solutions to mitigate the effects of NUMA.
Large Language Models (LLM) have gained a lot of attention given the recent technological advances. However, they require large memory requirement and high processing power, particularly for systems employing a limited amount of DRAM and slow storage devices. Often times, the data needed by the models cannot fit entirely in the main memória (DRAM), requiring external storage systems which…
(Only some records are available in English at this moment)
Persistent memory (PM) is a non-volatile byte-addressable memory technology that has good performance and fast response times, in the same order of magnitude as DRAM. Its persistence, however, presents many additional challenges to software, where transactions have been used as an essential mechanism.Current implementations like SPHT (Scalable Persistent Hardware Transactions) make use of…
In addition to loops, there are other hot-code regions that parallel programming tries to parallelize. Task-based programming model simplifies it by providing annotations of dependences between tasks. Thus, a runtime system manages these dependences and schedules tasks to execute on cores. However, the programmer must use directives (e.g. taskwait) to ensure control dependences between ta…
Recent microprocessors have incorporated transactions into their instruction set architecture (ISA). In this context, a transaction is a block of code that is executed in an all-or-nothing fashion, isolated from other transactions. Using the new ISA, programmers are allowed to delimit the instructions which make a transaction and the hardware is responsible to provide the transactional s…
(Only some records are available in English at this moment)