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Modeling of nanometric transistors for applications in analog circuits


The Silicon on insulator technology (Silicon-On-Insulator - SOI) has been constituted as an important alternative for the replacement of conventional MOS transistors, due to improvements such as reduced junction capacitance and larger carrier mobility in the channel region. Besides a significant improvement in the performance of digital circuits, the operation of SOI-MOS transistors in analog circuits also presents additional advantages such as better transconductance over drain current ratio. The combination of these characteristics has been expanding the range of use of SOI transistors in high-performance analog systems, achieving frequencies of the order of GHz and microwave applications, with wide applicability in telecommunications. As a solution to maintain the continuous reduction of the size of MOS transistors, reaching channel lengths of less than 25 nm, the use of more than one gate electrode have been widely considered academic community, still keeping the same benefits of CMOS structure with single gate, such as self-alignment of the source / drain regions. The MOS transistors with multiple gates, with two, three or four gates, are a promising alternative to solve the problems arising from the continuous reduction of the dimensions of MOS transistors due to the excellent control of the channel charges provided by these structures. In the literature, a lot of studies can be found with respect to the operation of these devices in digital circuits. However, few publications have demonstrated the excellent potential of these devices to be used in analog applications such as operational amplifiers, with performance superior to conventional planar MOS transistors. The research group coordinated by Prof. Antonio Cerdeira proposed a method to obtain the linearity characteristics of electronic devices and, more recently, an analytical model for double-gate transistors. This model was implemented in SPICE simulator, allowing the simulation of circuits using FinFET transistors, in collaboration with the group of FEI. With the aim of obtaining multiple gates structures with channel lengths even shorter new MOSFET structure has been proposed. The junctionless nanowire transistors, also called MOSFET with no junctions or gated resistor. In this new device a thin highly doped silicon nanowire is covered by the gate electrode, responsible for defining the channel length. Thus, the regions of source, channel and drain are made of the same dopant, there is no pn junction. In the case of an nMOS transistor, the three N-type regions would be, resulting in a structure N + N + B +. Papers were presented in the literature comparing the electrical properties of junctionless transistors for digital applications. However, the characteristics of analog transistors are still poorly explored and an analytical model for the simulation of analog circuits with these transistors is still lacking. In order to deepen the collaboration between the group coordinated by Prof. Dr. Marcelo Antonio Pavanello, FEI University Center, and coordinated by Prof. Dr. Antonio Cerdeira, the CINVESTAV, Mexico, we would like to foster the stay of Prof. Cerdeira for three months in the FEI University Center for the development of research in modeling of nanoscale MOS transistors of multiple gates in order to develop models that are integrated into circuit simulators. During his stay, Prof. Cerdeira also will teach a graduate course in the field of modeling of double gate MOSFETs at FEI that can be attended by graduate students from Sao Paulo State. (AU)