Code snippets identification for pipeline processing in FPGA accelerators for heterogeneous platforms

• Grant number: 14/14918-2
• Support Opportunities: Scholarships in Brazil - Doctorate (Direct)
• Start date: January 01, 2015
• End date: March 01, 2019
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Vanderlei Bonato
• Grantee: Leandro de Souza Rosa
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
• Associated scholarship(s): 16/13327-6 - Design space exploration on heterogeneous systems for high performance applications, BE.EP.DD

Abstract

High performance computing is an increasing field in computer sciences since the computational evolution in the last years has created systems that allow the acquisition of big data sets, opening the gap on how to process these data efficiently. Heterogeneous computing shows promising results dealing with such big sets of data by exploring parallel computations and the processors affinity of the computations. Between heterogeneous platforms, the most common are GPP and GPU working together, which has been explored for quite a few years and has reached a well advanced state of art, resulting in common commercial solutions. The usage of FPGAs is more recent and limited by the development complexity, but with good power efficiency and low latency results. In this project we propose technique to identify pipeline computations on high level sequential codes to be used on FPGAs accelerators creation in a heterogeneous platform, since such computations are efficiently mapped on FPGAs when compared with its implementations on graphic processors or multi-core architectures. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

ROSA, L. S.; DELBEM, A. C. B.; TOLEDO, C. F. M.; BONATO, V.. Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion. APPLIED SOFT COMPUTING, v. 49, p. 447-461, DEC 2016. (14/14918-2)

ROSA, LEANDRO DE SOUZA; BOUGANIS, CHRISTOS-SAVVAS; BONATO, VANDERLEI. Non-iterative SDC modulo scheduling for high-level synthesis. MICROPROCESSORS AND MICROSYSTEMS, v. 86, OCT 2021. (14/14918-2)

ROSA, LEANDRO DE SOUZA; BONATO, VANDERLEI; BOUGANIS, CHRISTOS-SAVVAS; IEEE. Scaling Up Loop Pipelining For High-Level Synthesis: A Non-Iterative Approach. 2018 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2018), v. N/A, p. 8-pg., 2018-01-01. (14/14918-2)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

ROSA, Leandro de Souza. Fast Code Exploration for Pipeline Processing in FPGA Accelerators. 2019. Doctoral Thesis - Universidade de São Paulo (USP). Instituto de Ciências Matemáticas e de Computação (ICMC/SB) São Carlos.