Modeling, Simulation and Fabrication of Analog Circuits with Asymmetric Self-Cascode SOI Transistors

• Grant number: 15/08616-6
• Support Opportunities: Scholarships in Brazil - Doctorate
• Start date: August 01, 2015
• End date: February 28, 2018
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits
• Principal Investigator: Michelly de Souza
• Grantee: Rafael Assalti
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil

Abstract

The Silicon-On-Insulator technology (SOI) has become a real alternative for the Complementary Metal-Oxide-Semiconductor technology (CMOS) implementation to conventional integrated circuits in a very large scale integration in both analog and digital applications. The SOI transistors have a series of advantages over the conventional MOS technology. However, these devices have reduced breakdown voltage due to the floating-body effect which causes the activation of the parasitic bipolar transistor associated with the MOS transistor. In order to minimize the occurrence of parasitic bipolar effects and improve the analog characteristics of SOI transistors, it has been designed a structure named as asymmetric self-cascode of SOI transistors. Several results demonstrate the great potential of this structure at device level and in analog applications.In this PhD work, it will be first studied the analog characteristics of asymmetric self-cascode with several dimensions, implemented with transistors from different technologies, such as planar and junctionless. It will be also performed experimental measurements of the low frequency noise of asymmetric self-cascode, as well as the drain current modeling, with the aim of allowing its use in a circuit simulator such as Eldo. Furthermore, it will be studied the impact of the asymmetric self-cascode in analog blocks, through two-dimensional and three-dimensional numerical simulations and circuits simulations. Finally, it will be designed, fabricated and characterized an operational amplifier implemented with asymmetric self-cascode of SOI transistors.

Scientific publications

(5)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

ASSALTI, RAFAEL; DE SOUZA, MICHELLY; FLANDRE, DENIS; IEEE. Linearity Enhancement in Asymmetric Self-Cascode Composed by FD SOI nMOSFETs. 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2018-01-01. (15/08616-6)

ASSALTI, R.; DE SOUZA, M.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; IEEE. Analog Performance of Self-Cascode SOI Nanowires nMOSFETs Aiming at Low-Power Applications. 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2017-01-01. (15/08616-6)

ASSALTI, R.; DE SOUZA, M.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; SARAFIS, P; NASSIOPOULOU, AG. Improved Analog Performance of SOI Nanowire nMOSFETs Self-Cascode through Back-Biasing. 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017), v. N/A, p. 4-pg., 2017-01-01. (15/08616-6)

ASSALTI, R.; DE SOUZA, M.; FLANDRE, D.; IEEE. Channel Width Influence on the Analog Performance of the Asymmetric Self-Cascode FD SOI nMOSFETs. 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS, v. N/A, p. 4-pg., 2017-01-01. (15/08616-6)

ASSALTI, R.; DORIA, R. T.; PAVANELLO, M. A.; DE SOUZA, M.; FLANDRE, D.; IEEE. Low-Frequency Noise in Asymmetric Self-Cascode FD SOI nMOSFETs. 2016 31ST SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2016-01-01. (15/08616-6)