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Electrical characterization and tridimensional simulation of nanowires MOS transistors

Grant number: 15/10491-7
Support type:Scholarships in Brazil - Doctorate
Effective date (Start): December 01, 2015
Effective date (End): May 31, 2018
Field of knowledge:Engineering - Electrical Engineering - Electrical Materials
Principal researcher:Marcelo Antonio Pavanello
Grantee:Bruna Cardoso Paz
Home Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil
Associated scholarship(s):16/06301-0 - Electrical characterization and tridimensional simulation of nanowires MOS transistors, BE.EP.DR

Abstract

The scaling of electronic devices has brought difficulties on using planar MOS transistors in extremely sub micrometric technologies due to the presence of short channel effects. Multiple gate MOS transistors increase significantly the gate control over the charges in the channel, reducing the occurrence of these effects. This is why these devices have shown to be of great interest for future technologies.Different multiple gate transistors such as double and triple gate FinFETs have earned attention in the scientific community due to their good behavior on digital applications. Recently developed, nanowire MOS transistors are another multiple gate structure that has shown promising results. These structures have a cross section of few nanometers, allowing excellent electrostatic control and reducing undesirable effects observed in MOS transistors with channel length as short as 10 nanometers.This research project aims to study the effect of temperature over electrical parameters of nanowires transistors, through numerical simulations and experimental measurements, in order to correlate the behavior of the devices with their physics. This analysis will be performed considering unstrained and strained silicon devices and different channel orientations. To reach the goals proposed in this work, tridimensional numerical simulations will be performed in short channel nanowires transistors as a function of temperature. The nanowires transistors that will be studied have been and will be fabricated a CEA-Leti, France. (AU)

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Scientific publications (5)
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
CERDEIRA, A.; ESTRADA, M.; PAVANELLO, M. A. On the compact modelling of Si nanowire and Si nanosheet MOSFETs. Semiconductor Science and Technology, v. 37, n. 2 FEB 1 2022. Web of Science Citations: 0.
PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs. Solid-State Electronics, v. 159, n. SI, p. 83-89, SEP 2019. Web of Science Citations: 0.
PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs. Solid-State Electronics, v. 149, p. 62-70, NOV 2018. Web of Science Citations: 0.
PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Electrical characterization of vertically stacked p-FET SOI nanowires. Solid-State Electronics, v. 141, p. 84-91, MAR 2018. Web of Science Citations: 3.
PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K. Solid-State Electronics, v. 128, n. SI, p. 60-66, FEB 2017. Web of Science Citations: 4.

Please report errors in scientific publications list by writing to: cdi@fapesp.br.