Numerous are the efforts in researches and high investments are currently made in order to the integrated circuits (ICs) can operate in high temperature (T) environment, without losing their electrical performance. Normally, the Bulk Complementary Metal-Oxide-Semiconductor (CMOS) ICs can operate satisfactorily at moderate temperatures (about 125 ºC), without losing their electrical performance. But, thanks to the advantages of Silicon-On-Insulator (SOI) technology, the operation range can be extended up to 300 ºC. Further to use other types of materials to achieve better electrical performance at high temperatures, there is an innovative approach, until still little explored by the scientific and business community, which is capable of using strategies of "Engineering of PN junction between the drain/source and channel regions of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)", or simply gate layout change. This new layout technique is able to add new effects to these structures, such as the Longitudinal Corner Effect (LCE), the PArallel connection of MOSFET with Different Channel Lengths Effect (PAMDLE), and Deactivate the Parasitic MOSFETs of the Bird's Beak Regions Effect (DEPAMBBRE), which are capable to improve their main analog and digital parameters and figures of merit. This layout strategy can be translated simply into the study of innovative layout gate structures (hexagonal, octagonal, circular etc.) for the implementation of MOSFETs, without causing any extra cost to the current CMOS ICs manufacturing process. The Ellipsoidal layout style is a possible alternative in this context, because it can to enhance the analog and digital electrical characteristics of a MOSFET. In this context, the objective this PhD research project is, for the first time, to investigate experimentally the effects of the high temperatures in the electric behavior of the Ellipsoidal MOSFET in relation to its respective conventional equivalent (rectangular gate geometry), regarding the same gates area (AG), the same channel widths (W) and geometric factors (fg=W/L, where L is the channel length). Additionally, the electrical performance of this innovative layout will be compared to the MOSFETs implemented with the hexagonal (Diamond) and octagonal (Octo) layouts styles, in order to identify what is better layout style for MOSFET which is capable of presenting the better electrical performance at high temperatures.
News published in Agência FAPESP Newsletter about the scholarship: