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High-level mapping framework for heterogeneous architectures with FPGAs and GPUs

Grant number: 18/22289-6
Support type:Scholarships abroad - Research Internship - Doctorate (Direct)
Effective date (Start): January 01, 2019
Effective date (End): December 31, 2019
Field of knowledge:Physical Sciences and Mathematics - Computer Science
Principal Investigator:Vanderlei Bonato
Grantee:Andre Bannwart Perina
Supervisor abroad: Dr Juergen Becker
Home Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
Local de pesquisa : Karlsruhe Institute of Technology (KIT), Germany  
Associated to the scholarship:16/18937-7 - Energy-aware design space exploration framework for heterogeneous architectures with FPGAs and GPUs, BP.DD

Abstract

To increase computing performance while keeping energy consumption to an acceptable budget, heterogeneous systems are currently investigated. By using dedicated compute units as accelerators to speedup specific parts of an application, hardware resources are better utilised resulting in a more energy efficient computing system. However, the task of performing such application mapping to accelerators is still a challenge, requiring knowledge beyond software domain in order to understand which part of the code fits better to the capability of the hardware available. Currently, there are tools supporting unified frontends and languages to simplify the programming of such heterogeneous systems, however there is still a high dependency of the user to manually perform the final mapping process. This work proposes to infer the most suitable regions of a high-level code to be mapped on FPGA or GPU through performance and power estimation. Furthermore, design space exploration is proposed for further performance optimisation, all performed without the need of time-consuming synthesis for FPGA.