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Vertical junctions based on two-dimensional materials and rolled-up nanomembranes for electronic applications

Grant number: 21/12499-6
Support Opportunities:Scholarships abroad - Research Internship - Post-doctor
Effective date (Start): August 01, 2022
Effective date (End): July 31, 2023
Field of knowledge:Physical Sciences and Mathematics - Physics - Condensed Matter Physics
Principal Investigator:Carlos César Bof Bufon
Grantee:Luíz Gustavo Simão Albano
Supervisor: Jiwoong Park
Host Institution: Centro Nacional de Pesquisa em Energia e Materiais (CNPEM). Ministério da Ciência, Tecnologia e Inovações (Brasil). Campinas , SP, Brazil
Research place: University of Chicago, United States  
Associated to the scholarship:17/25553-3 - Fabrication and characterization of self-rolled up nanomembranes of surface-supported metal-organic frameworks (SURMOFs) for applications in ultracompact electronic devices, BP.PD


Two-dimensional (2D) materials beyond graphene have achieved significant attention during recent years. Transition-metal dichalcogenides (TMDs), a special class of 2D materials with semiconducting character, exhibit a unique set combination of atomic-scale thickness, good mechanical properties, tailored bandgaps, and high mobilities. Advances covering the growth and deposition involving these materials have enabled the fabrication of electronic devices with outstanding performances. However, vertical junction compositions, an important building block for modern integrated circuitry, suffer from the inevitable chemical disorder and Fermi-level pinning when TMD monolayers are aimed using conventional methods of fabrication. Thus, novel integrative and damage-free approaches are still necessary to prepare highly integrated and robust vertical junctions based on TMDs. Therefore, this research proposal aims at the integration of TMD monolayers into rolled-up nanomembranes (rNMs)-based junctions. This method is based on the self-released of a strained metallic layer, performing a damage-free and self-adjusted top contact. Different TMD monolayers (MoS2, WS2, WSe2) will be integrated and characterized, focusing on the limits of an ideal out-of-plane metal-semiconductor junction. Then, the respective stacked heterostructures will also be integrated to form type-II heterojunctions (staggered gap). With the optimization, the demonstration of logic gates integrating devices will be performed. This original research proposal aims to promote a considerable advance towards the challenge of contacting TMDs without damage to build novel and scalable multifunctional devices.

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