Efficient Handling of Large Heap Allocation in Persistent Hardware Transactional Memory Systems

• Grant number: 22/11704-8
• Support Opportunities: Scholarships in Brazil - Master
• Start date: October 01, 2022
• End date: March 31, 2025
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Alexandro José Baldassin
• Grantee: André Libório de Barros Ferraz
• Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
• Associated research grant: 18/15519-5 - Performance optimizations for multicore architectures, AP.JP2
• Associated scholarship(s): 23/12624-0 - Gerenciamento Eficiente da Alocação de Grandes Áreas de Memória em Sistemas Transacionais com Memória Persistente, BE.EP.MS

Abstract

Persistent Memory (PM) is an emerging memory technology aimed to eliminate the gap between main memory and stable storage. Nevertheless, today's programs will not readily benefit from PM because crash failures may render the program in an unrecoverable and inconsistent state. In this context, persistent transactions (PTM) have been proposed as a mechanism to ease the adoption of PM by simplifying the task of programming such systems. Current high-performance PTM systems use hardware transactions (PHTM - Persistent Hardware Transactional Memory) to improve performance, but such support does not provide durability. As such, a lot of research have been proposed recently to address this issue by implementing durability in software, while retaining the improved performance provided by hardware transactions. This MSc. project seeks to advance the state-of-the-art of PHTM systems by devising a novel scheme to support large heap allocation. Current systems that use shadow paging drastically degrade performance because of the cost of swapping memory in and out of disk. Therefore, this investigation plans to work around that problem by proposing new techniques to reduce the cost of memory swapping.