Study of the transistors electrical behavior of 130 nm SOI CMOS technology for application in analog circuits

• Grant number: 24/16222-7
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: February 01, 2025
• End date: January 31, 2026
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Measurements, Instrumentation
• Principal Investigator: Paula Ghedini Der Agopian
• Grantee: Leonardo de Moraes Alvarenga
• Host Institution: Faculdade de Engenharia. Universidade Estadual Paulista (UNESP). Campus Experimental São João da Boa Vista. São João da Boa Vista , SP, Brazil

Abstract

With the continuous reduction of devices, the control of short-channel effects in conventional MOSFETs has become a problem for technological evolution. MOS transistors manufactured in SOI technology began to be used due to their excellent performance improvements, greater immunity to short-channel effects and higher switching speed.This project aims to study the electrical behavior of fully and partially depleted SOI MOSFET transistors and apply them in recurring analog blocks in the design of integrated circuits. This scientific initiation will be based on the DC electrical characterization of the transistors, where both basic and analog parameters of the transistors will be evaluated. These analyses will be performed through experimental measurements of these transistors and will be of fundamental importance for the calibration of the SPICE simulator where the amplifier circuits will be implemented. Very precise calibration will play a fundamental role in the analysis of how this nanometric technology will behave when applied to analog circuits. A comparison between amplifiers designed with partially depleted and fully depleted transistors will be made, taking it a step further than what is seen in the electrical engineering course.