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Marcelo Antonio Pavanello

CV Lattes GoogleMyCitations ResearcherID ORCID


Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). Centro Universitário da FEI (UNIFEI). Campus de São Bernardo do Campo  (Institutional affiliation for the last research proposal)
Birthplace: Brazil

bachelor's at Electric Engineering from Centro Universitário da FEI (1993), master's at Electric Engineering from Universidade de São Paulo (1996) and doctorate at Electric Engineering from Universidade de São Paulo (2000). Has experience in Electric Engineering, focusing on Materials and Components Semiconductors, acting on the following subjects: soi mosfet, gc soi mosfet, analog applications, low temperature and electrical characterization. (Source: Lattes Curriculum)

Research grants
Scholarships in Brazil
Scholarships abroad
FAPESP support in numbers * Updated April 10, 2021
Total / Available in English
Most frequent collaborators in research granted by FAPESP
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Use this Research Supported by FAPESP (BV/FAPESP) channel only to send messages referring to FAPESP-funded scientific projects.


 

 

 

 

Keywords used by the researcher
Scientific publications resulting from Research Grants and Scholarships under the grantee's responsibility (15)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

Publications15
Citations39
Cit./Article2.6
Data from Web of Science

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs. Solid-State Electronics, v. 159, n. SI, p. 83-89, . Web of Science Citations: 0. (15/10491-7)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. Junctionless nanowire transistors parameters extraction based on drain current measurements. Solid-State Electronics, v. 158, p. 37-45, . Web of Science Citations: 0. (14/18041-8)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs. Solid-State Electronics, v. 149, p. 62-70, . Web of Science Citations: 0. (15/10491-7)

DORIA, RODRIGO TREVISOLI; TREVISOLI, RENAN; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, n. SI, p. 17-20, . Web of Science Citations: 4. (14/18041-8)

PAZ, B. C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; AVILA-HERRERA, F.; CERDEIRA, A.; PAVANELLO, M. A.. Drain current model for short-channel triple gate junctionless nanowire transistors. MICROELECTRONICS RELIABILITY, v. 63, p. 1-10, . Web of Science Citations: 4. (12/24377-3, 14/13816-1)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; PAVANELLO, MARCELO ANTONIO. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, n. 2, p. 856-863, . Web of Science Citations: 9. (14/18041-8)

TREVISOLI, RENAN; DE SOUZA, MICHELLY; DORIA, RODRIGO TREVISOLI; KILCHTYSKA, VALERIYA; FLANDRE, DENIS; PAVANELLO, MARCELO ANTONIO. Junctionless nanowire transistors operation at temperatures down to 4.2K. Semiconductor Science and Technology, v. 31, n. 11, . Web of Science Citations: 4. (14/18041-8)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K. Solid-State Electronics, v. 128, n. SI, p. 60-66, . Web of Science Citations: 4. (15/10491-7)

TREVISOLI, RENAN; PAVANELLO, MARCELO ANTONIO; CAPOVILLA, CARLOS EDUARDO; BARRAUD, SYLVAIN; DORIA, RODRIGO TREVISOLI. Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 67, n. 6, p. 2536-2543, . Web of Science Citations: 0. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. MICROELECTRONIC ENGINEERING, v. 215, . Web of Science Citations: 0. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. Junctionless nanowire transistors parameters extraction based on drain current measurements. Solid-State Electronics, v. 158, p. 37-45, . Web of Science Citations: 0. (14/18041-8)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs. Solid-State Electronics, v. 149, p. 62-70, . Web of Science Citations: 0. (15/10491-7)

DORIA, RODRIGO TREVISOLI; TREVISOLI, RENAN; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, n. SI, p. 17-20, . Web of Science Citations: 4. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; PAVANELLO, MARCELO ANTONIO. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, n. 2, p. 856-863, . Web of Science Citations: 9. (14/18041-8)

TREVISOLI, RENAN; DE SOUZA, MICHELLY; DORIA, RODRIGO TREVISOLI; KILCHTYSKA, VALERIYA; FLANDRE, DENIS; PAVANELLO, MARCELO ANTONIO. Junctionless nanowire transistors operation at temperatures down to 4.2K. Semiconductor Science and Technology, v. 31, n. 11, . Web of Science Citations: 4. (14/18041-8)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

SOUZA, Michelly de. Modelagem, simulação e fabricação de circuitos analógicos com transistores SOI convencionais e de canal gradual operando em temperaturas criogênicas.. Tese (Doutorado) -  Escola Politécnica.  Universidade de São Paulo (USP).  São Paulo.  (05/00875-0

DORIA, Rodrigo Trevisoli. Operação analógica de transistores de múltiplas portas em função da temperatura.. Tese (Doutorado) -  Escola Politécnica.  Universidade de São Paulo (USP).  São Paulo.  (07/04439-6

DORIA, Renan Trevisoli. Operação e modelagem de transistores MOS sem junções.. Tese (Doutorado) -  Escola Politécnica.  Universidade de São Paulo (USP).  São Paulo.  (10/00537-6

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