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Renan Trevisoli Doria

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Ministério da Educação (Brasil). Universidade Federal do ABC (UFABC). Centro de Engenharia, Modelagem e Ciências Sociais Aplicadas (CECS)  (Institutional affiliation for the last research proposal)
Birthplace: Brazil

bachelor's at Electric Engineering from Centro Universitário da FEI (2007), master's at Electric Engineering from Centro Universitário da FEI (2010) and doctorate at Electric Engineering from Universidade de São Paulo (2013). Has experience in Electric Engineering, focusing on Materials and Components Semiconductors, acting on the following subjects: finfet, low temperature, series resistance, analytical model and double gate transistors. (Source: Lattes Curriculum)

Research grants
Scholarships in Brazil
FAPESP support in numbers * Updated April 10, 2021
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Most frequent collaborators in research granted by FAPESP
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Use this Research Supported by FAPESP (BV/FAPESP) channel only to send messages referring to FAPESP-funded scientific projects.


 

 

 

 

Keywords used by the researcher
Scientific publications resulting from Research Grants and Scholarships under the grantee's responsibility (10)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

Publications10
Citations28
Cit./Article2.8
Data from Web of Science

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; CASSE, MIKAEL; REIMBOLD, GILLES; FAYNOT, OLIVIER; GHIBAUDO, GERARD; PAVANELLO, MARCELO ANTONIO. A New Method for Series Resistance Extraction of Nanometer MOSFETs. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 64, n. 7, p. 2797-2803, . Web of Science Citations: 4. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; PAVANELLO, MARCELO ANTONIO. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors. MICROELECTRONIC ENGINEERING, v. 147, p. 23-26, . Web of Science Citations: 3. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. MICROELECTRONIC ENGINEERING, v. 215, . Web of Science Citations: 0. (14/18041-8)

PAVANELLO, MARCELO ANTONIO; TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY. Static and dynamic compact analytical model for junctionless nanowire transistors. JOURNAL OF PHYSICS-CONDENSED MATTER, v. 30, n. 33, . Web of Science Citations: 3. (14/18041-8)

DORIA, RODRIGO T.; FLANDRE, DENIS; TREVISOLI, RENAN; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.. Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures. Semiconductor Science and Technology, v. 32, n. 9, . Web of Science Citations: 1. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. Junctionless nanowire transistors parameters extraction based on drain current measurements. Solid-State Electronics, v. 158, p. 37-45, . Web of Science Citations: 0. (14/18041-8)

DORIA, RODRIGO TREVISOLI; TREVISOLI, RENAN; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, n. SI, p. 17-20, . Web of Science Citations: 4. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; PAVANELLO, MARCELO ANTONIO. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, n. 2, p. 856-863, . Web of Science Citations: 9. (14/18041-8)

TREVISOLI, RENAN; DE SOUZA, MICHELLY; DORIA, RODRIGO TREVISOLI; KILCHTYSKA, VALERIYA; FLANDRE, DENIS; PAVANELLO, MARCELO ANTONIO. Junctionless nanowire transistors operation at temperatures down to 4.2K. Semiconductor Science and Technology, v. 31, n. 11, . Web of Science Citations: 4. (14/18041-8)

TREVISOLI, RENAN; PAVANELLO, MARCELO ANTONIO; CAPOVILLA, CARLOS EDUARDO; BARRAUD, SYLVAIN; DORIA, RODRIGO TREVISOLI. Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 67, n. 6, p. 2536-2543, . Web of Science Citations: 0. (14/18041-8)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

DORIA, Renan Trevisoli. Operação e modelagem de transistores MOS sem junções.. Tese (Doutorado) -  Escola Politécnica.  Universidade de São Paulo (USP).  São Paulo.  (10/00537-6

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