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(Referência obtida automaticamente do Web of Science, por meio da informação sobre o financiamento pela FAPESP e o número do processo correspondente, incluída na publicação pelos autores.)

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

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Autor(es):
Pereira, A. S. N. [1] ; de Steel, G. [1] ; Planes, N. ; Haond, M. [2] ; Giacomini, R. ; Flandre, D. [1] ; Kilchytska, V.
Número total de Autores: 7
Afiliação do(s) autor(es):
[1] STMicroelectronics, Crolles - France
[2] Giacomini, R., Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo, Brazil. Planes, N., Kilchytska, V., Catholic Univ Louvain, ICTEAM, Louvain, Belgium. Pereira, A. S. N., STMicroelectronics, Crolles - France
Número total de Afiliações: 2
Tipo de documento: Artigo Científico
Fonte: Solid-State Electronics; v. 128, n. SI, p. 67-71, FEB 2017.
Citações Web of Science: 2
Resumo

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 degrees C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis' model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test. (C) 2016 Elsevier Ltd. All rights reserved. (AU)

Processo FAPESP: 14/11627-7 - Estudo e análise de modelos compactos para UTBB SOI MOSFETs
Beneficiário:Arianne Soares Do Nascimento Pereira
Linha de fomento: Bolsas no Exterior - Estágio de Pesquisa - Doutorado