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(Referência obtida automaticamente do Web of Science, por meio da informação sobre o financiamento pela FAPESP e o número do processo correspondente, incluída na publicação pelos autores.)

A Monolithic 32-Channel Front End and DSP ASIC for Gaseous Detectors

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Autor(es):
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Hernandez, Hugo [1] ; de Souza Sanches, Bruno Cavalcante [1] ; Carvalho, Dionisio [1] ; Bregant, Marco [2] ; Pabon, Armando Ayala [1] ; da Silva, Ronaldo Wilton [1] ; Hernandez, Raul Acosta [1] ; Weber, Tiago Oliveira [1] ; do Couto, Andre Luis [1] ; Campos, Arthur [1] ; Cubas, Heiner Alarcon [1] ; Martins, Tarciso A. [1] ; Munhoz, Marcelo G. [2] ; Van Noije, Wilhelmus [1]
Número total de Autores: 14
Afiliação do(s) autor(es):
[1] Univ Sao Paulo, Dept Elect Syst Engn, Escola Politecn, BR-05508010 Sao Paulo - Brazil
[2] Univ Sao Paulo, Inst Fis, BR-05508090 Sao Paulo - Brazil
Número total de Afiliações: 2
Tipo de documento: Artigo Científico
Fonte: IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT; v. 69, n. 6, 1, p. 2686-2697, JUN 2020.
Citações Web of Science: 0
Resumo

Conseil Europeen pour la Recherche Nucleaire is currently undergoing a major upgrade within the A Large Ion Collider Experiment (ALICE) detectors, one of the four main experiments at the Large Hadron Collider (LHC) accelerator. The LHC luminosity will increase making the heavy ions collision rate rise from 500 Hz to 50 kHz. Both the time projection chamber (TPC) and muon chamber (MCH) detectors demand a new and faster readout electronics, which support continuous readout to cope with this higher rate. This paper presents the serialized analog-digital multipurpose application-specific integrated circuit (ASIC) (SAMPA) integrated circuit for upgrading the TPC and MCH front-end and signal processing of charge induced signals, addressing the higher data rate specification. The SAMPA comprises 32 equal channels, twice the present ALICE TPC readout circuitry capacity. Each channel is composed of a positive/negative polarity charge sensitive amplifiers, a pulse shaper, and a 10-bit analog-to-digital converter. It also integrates a full custom digital signal processor, which receives the data from 32 channels, compensate signal perturbations or distortion through several filters and transmits the processed data. Designed for Taiwan Semiconductor Manufacturing Company 130-nm CMOS process, the manufactured chip occupies an area of approximately 85 mm(2) and consumes about 8.3 mW per channel at a nominal voltage supply of 1.25 V. The SAMPA is silicon proven and the experimental test results have confirmed its functionality and suitability for the ALICE Upgrade (2019-2020). (AU)

Processo FAPESP: 13/06885-4 - Projeto de um ASIC de aquisição e processamento digital de sinais para o time projection chamber do experimento ALICE
Beneficiário:Wilhelmus Adrianus Maria van Noije
Linha de fomento: Auxílio à Pesquisa - Regular
Processo FAPESP: 14/12664-3 - Desenvolvimento de instrumentação científica para o experimento ALICE do LHC-CERN
Beneficiário:Wilhelmus Adrianus Maria van Noije
Linha de fomento: Auxílio à Pesquisa - Projetos Especiais