SPHT: Scalable Persistent Hardware Transactions

Autor(es)

Castro, Daniel ; Baldassin, Alexandro ; Barreto, Joao ; Romano, Paolo ; USENIX Assoc

• Tipo de documento: Artigo Científico
• Fonte: PROCEEDINGS OF THE 19TH USENIX CONFERENCE ON FILE AND STORAGE TECHNOLOGIES (FAST '21); v. N/A, p. 15-pg., 2021-01-01.

Resumo

With the emergence of byte-addressable Persistent Memory (PM), a number of works have recently addressed the problem of how to implement persistent transactional memory using off-the-shelf hardware transactional memory systems. Using Intel Optane DC PM, we show, for the first time in the literature, experimental results highlighting several scalability bottlenecks of state of the art approaches, which so far have only been evaluated via PM emulation. We tackle these limitations by proposing SPHT (Scalable Persistent Hardware Transactions), an innovative Persistent Transactional Memory that exploits a set of novel mechanisms aimed at enhancing scalability both during transaction processing and recovery. We show that SPHT enhances throughput by up to 2.6x on STAMP and achieves speedups of up to 2.8x in the log replay phase vs. state of the art solutions. (AU)

• Processo FAPESP: 19/10471-7 - Explorando o máximo de memória transactional em hardware
• Beneficiário: Alexandro José Baldassin
• Modalidade de apoio: Bolsas no Exterior - Pesquisa
• Processo FAPESP: 18/15519-5 - Otimizações de desempenho para arquiteturas multicore
• Beneficiário: Alexandro José Baldassin
• Modalidade de apoio: Auxílio à Pesquisa - Jovens Pesquisadores - Fase 2