Autor(es)

Almeida, M. A. ; Pedrino, E. C. ; Nicoletti, M. C. ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2016 29TH SIBGRAPI CONFERENCE ON GRAPHICS, PATTERNS AND IMAGES (SIBGRAPI); v. N/A, p. 6-pg., 2016-01-01.

Resumo

A new and efficient automatic hybrid method, called Hy-EH, based on Virtual Reconfigurable Architectures (VRAs) and implemented in Field Programmable Gate Arrays (FPGAs) is proposed, for a hardware-embedded construction of image filters. The method also encompass an evolutionary software system, which represents the chromosome as a bi-dimensional grid of function elements (FEs), entirely parameterized using the Verilog-HDL (Verilog Hardware Description Language), which is reconfigured using the MATLAB toolbox GPLAB, before its download into the FPGA. In the so-called intrinsic proposals, evolutionary processes take place internally to the hardware, in a pre-defined fixed way; in extrinsic proposals evolutionary processes happen externally to the hardware. The hybrid Hy-EH method, described in this paper allows for the intrinsic creation of a flexible-sized hardware, in an extrinsic way i.e., by means of an evolutionary process that happens externally to the hardware. Hy-EH is also a convenient choice as far as extrinsic methods are considered, since it does not depend on a proprietary solution for its implementation. A comparative analysis of using the Hy-EH versus an existing intrinsic proposal, in two well-known problems, has been conducted. Results show that by using Hy-EH there was little hardware complexity due to the optimized and more flexible use of shorter chromosomes. (AU)

• Processo FAPESP: 15/23297-4 - Sistema para geração automática de hardware em FPGAs por programação genética cartesiana
• Beneficiário: Emerson Carlos Pedrino
• Modalidade de apoio: Auxílio à Pesquisa - Regular