Linearity Enhancement in Asymmetric Self-Cascode Composed by FD SOI nMOSFETs

Autor(es)

Assalti, Rafael ; de Souza, Michelly ; Flandre, Denis ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO); v. N/A, p. 4-pg., 2018-01-01.

Resumo

In this paper, the linearity of the Asymmetric Self-Cascode composed by Fully Depleted SOI nMOSFETs is experimentally evaluated, using transistors with different channel lengths. The abnormal (flat) transconductance of this composite transistor is used to promote a linearity enhancement. Disregarding the gain, the minimum harmonic distortion for low-power low-voltage applications has been obtained for the shortest transistor near the source and longest transistor near the drain. (AU)

• Processo FAPESP: 15/08616-6 - Modelagem, Simulação e Fabricação de Circuitos Analógicos com Associação Série Assimétrica de Transistores SOI
• Beneficiário: Rafael Assalti
• Modalidade de apoio: Bolsas no Brasil - Doutorado