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(Referência obtida automaticamente do Web of Science, por meio da informação sobre o financiamento pela FAPESP e o número do processo correspondente, incluída na publicação pelos autores.)

Evaluation of digital methods for energy calculation and timing pick-off in positron emission tomography

Texto completo
Autor(es):
Murata, H. M. [1] ; Moralles, M. [2] ; Bonifacio, D. A. B. [1]
Número total de Autores: 3
Afiliação do(s) autor(es):
[1] CNEN RJ, IRD, Ave Salvador Allende S-N, BR-22783127 Rio De Janeiro, RJ - Brazil
[2] CNEN SP, IPEN, Ave Lineu Prestes 2242, BR-05422970 Sao Paulo, SP - Brazil
Número total de Afiliações: 2
Tipo de documento: Artigo Científico
Fonte: Journal of Instrumentation; v. 13, SEP 2018.
Citações Web of Science: 1
Resumo

Traditionally, pulse processing in Positron Emission Tomography (PET) has been based on analog or discrete circuits forming a decentralized processing system. However, there is a convergence for digital and integrated implementations due to the characteristics of the modern electronic devices which are real-time processing capable, such as Application-Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) with fast Analog to Digital Converters (ADC). However, FPGA can provide fast implementation at relatively low cost and also enables the development of sophisticated digital pulse processing algorithms to improve energy, position and time resolutions in PET systems. Our group has developed and evaluated one energy calculation and three timing pick-off methods for implementation onto an FPGA-based system. For a typical PET detector setup, our charge integration method presents energy resolution similar to previously designed PET detectors. The best performance for timing pick-off was achieved by the Initial Rise Interpolation (IRI) method, where a coincidence time resolution of around 440 ps is suitable for Time of Flight (TOF) PET. Future works include embedding the proposed algorithms in a FPGA-based data acquisition system under development by our group which will be employed in a PET prototype. (AU)

Processo FAPESP: 16/21345-4 - Desenvolvimento de algoritmos para FPGA (Field Programmable Gate Array)
Beneficiário:Helio Massaharu Murata
Modalidade de apoio: Bolsas no Brasil - Programa Capacitação - Treinamento Técnico