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(Referência obtida automaticamente do Web of Science, por meio da informação sobre o financiamento pela FAPESP e o número do processo correspondente, incluída na publicação pelos autores.)

Class-specific early exit design methodology for convolutional neural networks

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Autor(es):
Bonato, Vanderlei [1] ; Bouganis, Christos-Savvas [2]
Número total de Autores: 2
Afiliação do(s) autor(es):
[1] Univ Sao Paulo, Inst Math & Comp Sci, Sao Carlos, SP - Brazil
[2] Imperial Coll London, Dept Elect & Elect Engn, London - England
Número total de Afiliações: 2
Tipo de documento: Artigo Científico
Fonte: APPLIED SOFT COMPUTING; v. 107, AUG 2021.
Citações Web of Science: 0
Resumo

Convolutional Neural Network-based (CNN) inference is a demanding computational task where a long sequence of operations is applied to an input as dictated by the network topology. Optimisations by data quantisation, data reuse, network pruning, and dedicated hardware architectures have a strong impact on reducing both energy consumption and hardware resource requirements, and on improving inference latency. Implementing new applications from established models available from both academic and industrial worlds is common nowadays. Further optimisations by preserving model architecture have been proposed via early exiting approaches, where additional exit points are included in order to evaluate classifications of samples that produce feature maps with sufficient evidence to be classified before reaching the final model exit. This paper proposes a methodology for designing early-exit networks from a given baseline model aiming to improve the average latency for a targeted subset class constrained by the original accuracy for all classes. Results demonstrate average time saving in the order of 2.09x to 8.79x for dataset CIFAR10 and 15.00x to 20.71x for CIFAR100 for baseline models ResNet-21, ResNet-110, Inceptionv3-159, and DenseNet-121. (C) 2021 Elsevier B.V. All rights reserved. (AU)

Processo FAPESP: 19/05286-6 - Exploração de uma infraestrutura de hardware baseada em FPGA para construção de DNN de ultra baixa latência
Beneficiário:Vanderlei Bonato
Modalidade de apoio: Bolsas no Exterior - Pesquisa