Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

Autor(es)

Banin Junior, Jose Roberto ^[1] ; de Lima Moreto, Rodrigo Alves ^[1] ; da Silva, Gabriel Augusto ^[1] ; Thomaz, Carlos Eduardo ^[1] ; Gimenez, Salvador Pinillos ^[1]

Afiliação do(s) autor(es)

^[1] FEI Univ Ctr, Dept Elect Engn, Av Humberto Alencar Castelo Branco 3972, BR-09850901 Sao Bernardo Do Campo, SP - Brazil

• Tipo de documento: Artigo Científico
• Fonte: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING; v. 106, n. 1, p. 293-306, JAN 2021.
• Citações Web of Science: 1

Resumo

This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (a) equal to 45 degrees, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness. (AU)

• Processo FAPESP: 18/21341-4 - Protótipo de inteligência computacional interativa para projeto e otimização de circuitos integrados analógicos
• Beneficiário: Rodrigo Alves de Lima Moreto
• Modalidade de apoio: Auxílio à Pesquisa - Pesquisa Inovativa em Pequenas Empresas - PIPE