Improved Analog Performance of SOI Nanowire nMOSFETs Self-Cascode through Back-Biasing

Autor(es)

Assalti, R. ; de Souza, M. ; Casse, M. ; Barraud, S. ; Reimbold, G. ; Vinet, M. ; Faynot, O. ; Sarafis, P ; Nassiopoulou, AG

• Tipo de documento: Artigo Científico
• Fonte: 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017); v. N/A, p. 4-pg., 2017-01-01.

Resumo

In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated. (AU)

• Processo FAPESP: 15/08616-6 - Modelagem, Simulação e Fabricação de Circuitos Analógicos com Associação Série Assimétrica de Transistores SOI
• Beneficiário: Rafael Assalti
• Modalidade de apoio: Bolsas no Brasil - Doutorado