Analog Performance of Self-Cascode SOI Nanowires nMOSFETs Aiming at Low-Power Applications

Autor(es)

Assalti, R. ; de Souza, M. ; Casse, M. ; Barraud, S. ; Reimbold, G. ; Vinet, M. ; Faynot, O. ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2017-01-01.

Resumo

This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages. (AU)

• Processo FAPESP: 15/08616-6 - Modelagem, Simulação e Fabricação de Circuitos Analógicos com Associação Série Assimétrica de Transistores SOI
• Beneficiário: Rafael Assalti
• Modalidade de apoio: Bolsas no Brasil - Doutorado