Evaluation of aspect-oriented compilation and synthesis for heterogeneous FPGA-based high-performance computing

• Processo: 13/50383-3
• Modalidade de apoio: Auxílio à Pesquisa - Regular
• Data de Início da vigência: 01 de outubro de 2013
• Data de Término da vigência: 31 de dezembro de 2014
• Área do conhecimento: Ciências Exatas e da Terra - Ciência da Computação - Sistemas de Computação
• Acordo de Cooperação: University of Southern California
• Pesquisador responsável: Vanderlei Bonato
• Beneficiário: Vanderlei Bonato
• Pesquisador Responsável no exterior: Pedro Diniz
• Instituição Parceira no exterior: University of Southern California (USC), Estados Unidos
• Instituição Sede: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brasil
• Vinculado ao auxílio: 13/07375-0 - CeMEAI - Centro de Ciências Matemáticas Aplicadas à Indústria, AP.CEPID
• Assunto(s): Computação de alto desempenho Algoritmos genéticos Computação reconfigurável Circuitos FPGA
• Palavra(s)-Chave do Pesquisador: Co Design Hw Sw | Fpga | Hardware Accelerator | Hpc

Resumo

High-Performance Computing (HPC) is at the core of many scientific and engineering challenges and is making a tremendous impact on modern-day life. Technological improvements and increased clock rates have meant that today's modem computers have impressive sustained concurrent computations with aggregate Peta-flop calculations rates. Despite this, the rate of improvement has reached a plateau due to energy and resilience issues. The base cores of these machines exhibit fairly low computational efficiencies and further performance and energy gains are slim at best. The move to highly concurrent machines increases not only the energy requirements for these large-scale machines but also exacerbate the difficulty in effectively programing them. As a result both performance and programs are highly non-portable. The proposed project aims at integrating and evaluating the applicability of a novel aspect-oriented approach for the implementation of genetic algorithm in the compilation and synthesis system approach for FPGA-based platforms. These genetic mapping algorithms are geared towards the exploration of the vast design spaces that are derived from the use of a wide range of high-level code and mapping transformations. In particular we will focus on transformation for resilience and real-time aspects in high-performance robotics computations such as image processing for feature recognition. (AU)