Hardware implementation and performance evaluation of the fast adaptive single-phase auto reclosing algorithm

Autor(es)

Dias, Ozenir ^[1] ; Tavares, Maria Cristina ^[1] ; Magrin, Fabiano ^[2]

Afiliação do(s) autor(es)

^[1] Univ Estadual Campinas, Sch Elect & Comp Engn, Campinas, SP - Brazil

^[2] Fed Univ Technol Parana UTFPR, Curitiba, Parana - Brazil

• Tipo de documento: Artigo de Revisão
• Fonte: Electric Power Systems Research; v. 168, p. 169-183, MAR 2019.
• Citações Web of Science: 0

Resumo

This study describes the hardware implementation of a fast adaptive single-phase auto reclosing algorithm based on voltage harmonic content measurement. The proposed algorithm classifies the fault type, preventing re closing onto permanent fault, and identifies the arc extinction instant, adjusting dead-time to implement re closing with granted success. The hardware was connected to the Real Time Digital Simulator (RTDS) to perform tests in hardware-in-the-loop (HIL) with a protective relay. The studied system is based on a 500 kV transmission line of the Brazilian electrical power system and eventually real case oscillograms were tested. The algorithm performance was validated with previous software development. However, in the present document we highlight the importance to implement hardware test, as operational limits can only be identified in this last testing stage. Robustness of proposed algorithm based on low-order voltage harmonic content was proved with oscillograms' tests. (AU)

• Processo FAPESP: 17/17228-5 - Análise e desenvolvimento de um algoritmo de religamento monopolar adaptativo rápido para linhas de transmissão de meio comprimento de onda
• Beneficiário: Ozenir Farah da Rocha Dias
• Modalidade de apoio: Bolsas no Brasil - Pós-Doutorado
• Processo FAPESP: 17/20010-1 - Contribuição para estudos das alternativas para transmissão a muito longa distância e proteção de sistemas de potência
• Beneficiário: Maria Cristina Dias Tavares
• Modalidade de apoio: Auxílio à Pesquisa - Regular