Hardware implementation and performance evaluation of the fast adaptive single-phase auto reclosing algorithm

Author(s)

Dias, Ozenir ^[1] ; Tavares, Maria Cristina ^[1] ; Magrin, Fabiano ^[2]

Affiliation

^[1] Univ Estadual Campinas, Sch Elect & Comp Engn, Campinas, SP - Brazil

^[2] Fed Univ Technol Parana UTFPR, Curitiba, Parana - Brazil

• Document type: Review article
• Source: Electric Power Systems Research; v. 168, p. 169-183, MAR 2019.
• Web of Science Citations: 0

Abstract

This study describes the hardware implementation of a fast adaptive single-phase auto reclosing algorithm based on voltage harmonic content measurement. The proposed algorithm classifies the fault type, preventing re closing onto permanent fault, and identifies the arc extinction instant, adjusting dead-time to implement re closing with granted success. The hardware was connected to the Real Time Digital Simulator (RTDS) to perform tests in hardware-in-the-loop (HIL) with a protective relay. The studied system is based on a 500 kV transmission line of the Brazilian electrical power system and eventually real case oscillograms were tested. The algorithm performance was validated with previous software development. However, in the present document we highlight the importance to implement hardware test, as operational limits can only be identified in this last testing stage. Robustness of proposed algorithm based on low-order voltage harmonic content was proved with oscillograms' tests. (AU)

• FAPESP's process: 17/17228-5 - ANALYSIS AND DEVELOPMENT OF A FAST ADAPTIVE SINGLE-PHASE RECLOSING ALGORITHM FOR HALF WAVELENGTH TRANSMISSION LINES
• Grantee: Ozenir Farah da Rocha Dias
• Support Opportunities: Scholarships in Brazil - Post-Doctoral
• FAPESP's process: 17/20010-1 - CONTRIBUTIONS TO VERY LONG TRANSMISSION SYSTEM AND POWER SYSTEM PROTECTION
• Grantee: Maria Cristina Dias Tavares
• Support Opportunities: Regular Research Grants