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Hardware implementation of genetic algorithms for automatic construction of image filters

Grant number: 15/24900-6
Support type:Scholarships in Brazil - Scientific Initiation
Effective date (Start): August 01, 2016
Effective date (End): July 31, 2017
Field of knowledge:Physical Sciences and Mathematics - Computer Science - Computing Methodologies and Techniques
Principal researcher:Emerson Carlos Pedrino
Grantee:Bruno Cezar de Padua
Home Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos , SP, Brazil

Abstract

In this research project, we propose the use of genetic algorithms for efficient solutions of automatic image filter construction. Thus, we intend to implement a genetic module in hardware (FPGA) in order to increase the performance of the evolution of these algorithms to solve the automatic filter construction problem. Such an approach may be useful to complement the contents of several fields of the course of Computer Engineering, besides being an additional learning of tools used by designers of hardware systems. Initially, the proposed architecture is modeled using MATLAB software, which allows you to work using genetic algorithms to create an evolutionary system, in order to validate the stages of the proposed architecture design process. After the system is ready, then it will be implemented in hardware in the FPGA (field-programmable gate array) using a hardware description language, for example, Verilog-HDL. Finally, all the implemented system will undergo tests to ensure it works and it is able to find effective solutions for the proposed problem. Thus, comparisons will be performed with algorithms in software as with other similar implementations in hardware for validation of the proposal.

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