System for automatic hardware generation in FPGAs by Cartesian Genetic Programming

• Grant number: 15/23297-4
• Support type: Regular Research Grants
• Duration: March 01, 2016 - February 28, 2018
• Field of knowledge: Physical Sciences and Mathematics - Computer Science
• Principal Investigator: Emerson Carlos Pedrino
• Grantee: Emerson Carlos Pedrino
• Home Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos , SP, Brazil

Abstract

In this research project it is aimed to develop an automated system for generating digital circuits, dedicated to a given application, to be implemented in FPGA, based on the technique known as Cartesian Genetic Programming (CGP). By Considering that the best performance for a given algorithm is only achieved when it is implemented in hardware, such an approach may be useful as a complementary tool for introductory courses in Digital Systems in undergraduate courses in the area, for research in Computer Architecture area, besides being an important tool for designers hardware systems in general. Initially, the evolutionary system able to solve problems will be developed and simulated in MATLAB software. By using the technique of Cartesian Genetic Programming, the program will generate primitive logic blocks such as AND gates, OR, and NOT, and Flip-Flops (phenotypes). From the generated initial setup, the system performs a search in the space of possible compositions of primitive logical operators, trying to find a path between the inputs and desired outputs composing, thus, the equivalent circuit corresponding to the user-desired application. Such a program will be presented in the form of an indexed graph, being encoded as a sequence of integers that indicate connections between logic blocks, besides the logical functions performed by these. Subsequently, the solution presented by the evolvable system will be converted in a flexible and automatic solution onto a reconfigurable hardware architecture, by means of a Hardware Description Language (VHDL or Verilog), for implementation in a FPGA (Field-Programmable Gate Array). Therefore, it is intended to create an intelligent system that generates digital circuits automatically to be implemented directly in FPGAs. Applications examples for this type of system are diverse and among them are: automatic generation of image and signal filters, state machines, computer architecture, systems for precision agriculture, just to name a few. (AU)

Scientific publications

(4)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

PEDRINO, EMERSON CARLOS; YAMADA, THIAGO; LUNARDI, THIAGO REGINATO; DE MELO VIEIRA, JR., JOSE CARLOS. Islanding detection of distributed generation by using multi-gene genetic programming based classifier. APPLIED SOFT COMPUTING, v. 74, p. 206-215, JAN 2019. Web of Science Citations: 1.

ALMEIDA, M. A.; PEDRINO, E. C. Hybrid Evolvable Hardware for automatic generation of image filters. Integrated Computer-Aided Engineering, v. 25, n. 3, p. 289-303, 2018. Web of Science Citations: 2.

PEDRINO, EMERSON CARLOS; GALLON, IGOR FELIPE; VALENTE, FREDY JOAO; FERNANDES, MARCIO MERINO; OGASHAWARA, OSMAR; RODA, VALENTIN OBAC. A Novel Methodology for Automated Generation of Flexible Hardware Architectures. PRZEGLAD ELEKTROTECHNICZNY, v. 94, n. 4, p. 17-21, 2018. Web of Science Citations: 0.

PIHON, P. E.; PEDRINO, E. C.; RODA, V. O.; NICOLETTI, M. C. A hardware oriented ad-hoc computer-based method for binary structuring element decomposition based on genetic algorithms. Integrated Computer-Aided Engineering, v. 23, n. 4, p. 369-383, 2016. Web of Science Citations: 9.