Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures

Autor(es)

Cerdeira, Antonio ; Estrada, Magali ; Mariniello Da Silva, Genaro ; Calcade Rodrigues, Jaime ; Pavanello, Marcelo A. ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC); v. N/A, p. 4-pg., 2022-01-01.

Resumo

In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data. (AU)

• Processo FAPESP: 19/15500-5 - Simulação atomística das propriedades elétricas de nanofios transistores MOS
• Beneficiário: Marcelo Antonio Pavanello
• Modalidade de apoio: Auxílio à Pesquisa - Regular