| Texto completo | |
| Autor(es): |
de Souza, Michelly
;
Rodrigues, Jaime Calcade
;
Mariniello, Genaro
;
Casse, Mikael
;
Barraud, Sylvain
;
Vinet, Maud
;
Faynot, Olivier
;
Pavanello, Marcelo A.
;
IEEE
Número total de Autores: 9
|
| Tipo de documento: | Artigo Científico |
| Fonte: | 2022 IEEE 15TH WORKSHOP ON LOW TEMPERATURE ELECTRONICS (WOLTE 2022); v. N/A, p. 4-pg., 2022-01-01. |
| Resumo | |
In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry. (AU) | |
| Processo FAPESP: | 19/15500-5 - Simulação atomística das propriedades elétricas de nanofios transistores MOS |
| Beneficiário: | Marcelo Antonio Pavanello |
| Modalidade de apoio: | Auxílio à Pesquisa - Regular |