Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor

Autor(es)

Morais, Lucas ; Silva, Vitor ; Goldman, Alfredo ; Alvarez, Carlos ; Bosch, Jaume ; Frank, Michael ; Araujo, Guido ; Assoc Comp Machinery

• Tipo de documento: Artigo Científico
• Fonte: MICRO'52: THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE; v. N/A, p. 12-pg., 2019-01-01.

Resumo

Task Parallelism is a parallel programming model that provides code annotation constructs to outline tasks and describe how their pointer parameters are accessed so that they might be executed in parallel, and asynchronously, by a runtime capable of inferring and honoring their data dependence relationships. It is supported by several parallelization frameworks, as OpenMP and StarSs. Overhead related to automatic dependence inference and to the scheduling of ready-to-run tasks is a major performance limiting factor of Task Parallel systems. To amortize this overhead, programmers usually trade the higher parallelism that could be leveraged from finer-grained work partitions for the higher runtime-efficiency of coarser-grained work partitions. Such problems are even more severe for systems with many cores, as the task spawning frequency required for preserving cores from starvation grows linearly with their number. To mitigate these problems, researchers have designed hardware accelerators to improve runtime performance. Nevertheless, the high CPU-accelerator communication overheads of these solutions hampered their gains. We thus propose a RISC-V based architecture that minimizes communication overhead between the HW Task Scheduler and the CPU by allowing Task Scheduling software to directly interact with the former through custom instructions. Empirical evaluation of the architecture is made possible by an FPGA prototype featuring an eight-core Linux-capable Rocket Chip implementing such instructions. To evaluate the prototype performance, we both (1) adapted Nanos, a mature Task Scheduling runtime, to benefit from the new task-scheduling-accelerating instructions; and (2) developed Phentos, a new HW-accelerated light weight Task Scheduling runtime. Our experiments show that task parallel programs using Nanos-RV the Nanos version ported to our system are on average 2.13 times faster than those being serviced by baseline Nanos, while programs running on Phentos are 13.19 times faster, considering geometric means. Using eight cores, Nanos-RV is able to deliver speedups with respect to serial execution of up to 5.62 times, while Phentos produces speedups of up to 5.72 times. (AU)

• Processo FAPESP: 17/02682-2 - Projetando uma arquitetura manycore com suporte nativo a paralelismo baseado em tarefas
• Beneficiário: Lucas Henrique Morais
• Modalidade de apoio: Bolsas no Brasil - Mestrado
• Processo FAPESP: 14/25694-8 - Paralelização de laços usando map-reduce na nuvem para cargas de trabalho científicas
• Beneficiário: Hervé Yviquel
• Modalidade de apoio: Bolsas no Brasil - Pós-Doutorado
• Processo FAPESP: 18/00687-0 - Adicionando suporte nativo de escalonamento de tarefas a um processador rocket chip RISC-V multi-core
• Beneficiário: Lucas Henrique Morais
• Modalidade de apoio: Bolsas no Exterior - Estágio de Pesquisa - Mestrado