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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

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Autor(es):
de Souza, Michelly ; Cerdeira, Antonio ; Estrada, Magali ; Casse, Mikael ; Barraud, Sylvain ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo A.
Número total de Autores: 8
Tipo de documento: Artigo Científico
Fonte: Solid-State Electronics; v. 208, p. 4-pg., 2023-10-01.
Resumo

This paper presents an experimental assessment of gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors for different temperatures of operation, in the temperature range between 300 K and 580 K. The temperature rise increases the GIDL current and its dependence on the device width due to the increase of band-to-band generation with temperature and weakening of electrostatic coupling. (AU)

Processo FAPESP: 19/15500-5 - Simulação atomística das propriedades elétricas de nanofios transistores MOS
Beneficiário:Marcelo Antonio Pavanello
Modalidade de apoio: Auxílio à Pesquisa - Regular
Processo FAPESP: 23/03006-1 - EUROSOI-ULIS 2023 - Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
Beneficiário:Michelly de Souza
Modalidade de apoio: Auxílio à Pesquisa - Reunião - Exterior