Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model

Autor(es)

Moreira, Claudio V. ; Trevisoli, Renan ; Pavanello, Marcelo Antonio ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2019 LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC); v. N/A, p. 4-pg., 2019-01-01.

Resumo

This paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement. (AU)

• Processo FAPESP: 14/18041-8 - Caracterização elétrica e modelagem de dispositivos eletrônicos avançados
• Beneficiário: Renan Trevisoli Doria
• Modalidade de apoio: Bolsas no Brasil - Pós-Doutorado