| Texto completo | |
| Autor(es): |
Linhares, Alisson
;
Rusa, Henrique
;
Formiga, Daniel
;
Azevedo, Rodol Fo
;
IEEE
Número total de Autores: 5
|
| Tipo de documento: | Artigo Científico |
| Fonte: | 33RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2020); v. N/A, p. 6-pg., 2020-01-01. |
| Resumo | |
Common hardware design specifications usually describe the worst case scenario to improve fault tolerance and the quality of the final product. When taken to extreme, this approach can also lead to hardware overestimation, resulting on extra logic which, in real scenarios, may never be exercised. In this paper, we propose a SystemC profiling framework to help developers improve fixed-point hardware utilization by reporting unused bits and providing insights on data usage through the source code. We tested our framework against a set of publicly available synthesizable benchmarks (S2CBench), obtaining improvements in latency and area, demonstrating the potential of this technology. We also show a case study based on a proprietary Digital Signal Processor block that had their configurations tuned, for a year, by a group of specialist designers. According to our analysis, the methodology presented in this paper reduced bit requirements on some intermediate computations as much as 55.6%, reducing the energy consumption by 2.46%. (AU) | |
| Processo FAPESP: | 13/08293-7 - CECC - Centro de Engenharia e Ciências Computacionais |
| Beneficiário: | Munir Salomao Skaf |
| Modalidade de apoio: | Auxílio à Pesquisa - Centros de Pesquisa, Inovação e Difusão - CEPIDs |