| Texto completo | |
| Autor(es): |
Número total de Autores: 3
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| Afiliação do(s) autor(es): | [1] Univ Estadual Paulista, UNESP, Rio Claro - Brazil
[2] Univ Estadual Campinas, UNICAMP, Campinas, SP - Brazil
Número total de Afiliações: 2
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| Tipo de documento: | Artigo Científico |
| Fonte: | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING; v. 72, n. 12, p. 1535-1546, DEC 2012. |
| Citações Web of Science: | 2 |
| Resumo | |
Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention but developing applications for such architectures is not an easy task due to the lack of appropriate tools and programming models. We present the design of a runtime system for the Cell/BE architecture that works with memory transactions. Transactional programs are automatically instrumented by the compiler, shortening development time and avoiding synchronization mistakes usually present in lock-based approaches (such as deadlock). Experimental results conducted with a prototype implementation and the STAMP benchmark show good scalability for applications with moderate to low contention levels, and whose transactions are not too small. For those cases in which a small performance loss is admissible, we believe that the ease of programming provided by transactions greatly pays off. (C) 2012 Elsevier Inc. All rights reserved. (AU) | |
| Processo FAPESP: | 11/19373-6 - Entendendo e explorando a correlação energia/desempenho em algoritmos concorrentes |
| Beneficiário: | Alexandro José Baldassin |
| Modalidade de apoio: | Auxílio à Pesquisa - Jovens Pesquisadores |