Application-oriented cache memory configuration for energy efficiency in multi-cores

Autor(es)

Silva, Bruno de Abreu ^[1] ; Cuminato, Lucas A. ^[1] ; Delbem, Alexandre C. B. ^[1] ; Diniz, Pedro C. ^[2] ; Bonato, Vanderlei ^[1]

Afiliação do(s) autor(es)

^[1] Univ Sao Paulo, Inst Math & Comp Sci ICMC, Sao Carlos, SP - Brazil

^[2] Univ So Calif, Inst Informat Sci, Marina Del Rey, CA - USA

• Tipo de documento: Artigo Científico
• Fonte: IET COMPUTERS AND DIGITAL TECHNIQUES; v. 9, n. 1, p. 73-81, JAN 2015.
• Citações Web of Science: 5

Resumo

This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data-mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time. (AU)

• Processo FAPESP: 11/10163-9 - Otimização da relação desempenho/consumo de energia em arquiteturas multicore híbridas reconfiguráveis
• Beneficiário: Bruno de Abreu Silva
• Modalidade de apoio: Bolsas no Brasil - Doutorado