| Full text | |
| Author(s): |
Silva, Bruno de Abreu
[1]
;
Cuminato, Lucas A.
[1]
;
Delbem, Alexandre C. B.
[1]
;
Diniz, Pedro C.
[2]
;
Bonato, Vanderlei
[1]
Total Authors: 5
|
| Affiliation: | [1] Univ Sao Paulo, Inst Math & Comp Sci ICMC, Sao Carlos, SP - Brazil
[2] Univ So Calif, Inst Informat Sci, Marina Del Rey, CA - USA
Total Affiliations: 2
|
| Document type: | Journal article |
| Source: | IET COMPUTERS AND DIGITAL TECHNIQUES; v. 9, n. 1, p. 73-81, JAN 2015. |
| Web of Science Citations: | 5 |
| Abstract | |
This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data-mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time. (AU) | |
| FAPESP's process: | 11/10163-9 - Power-performance optimization in reconfigurable multi-core architectures composed by heterogeneous micro-architectures |
| Grantee: | Bruno de Abreu Silva |
| Support Opportunities: | Scholarships in Brazil - Doctorate |