|Support type:||Scholarships in Brazil - Master|
|Effective date (Start):||September 01, 2010|
|Effective date (End):||July 31, 2011|
|Field of knowledge:||Physical Sciences and Mathematics - Computer Science - Computer Systems|
|Principal Investigator:||Guido Costa Souza de Araújo|
|Grantee:||André Oliveira Loureiro Do Baixo|
|Home Institution:||Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil|
This work proposes an architecture model that enables the parallel execution of loop iterations in multicore architectures, using DOPIPE based compilation techniques (e.g. DSWP). The proposed architecture supports runtime detection of sequential consistency violations, across parallel loop iterations, while allowing for light- weight commit and squash operations. This is achieved by adding extra tag bits to the cache, and a small separate logic. No changes on pre-existing cache-coherence protocols are required. The impact of the extra cache bits is fairly small, and can be amortized as transistor count continues to increase. To evaluate such impact, cache size requirements per iteration have been measured for SPEC CINT 2000 loops, revealing a dynamic footprint compatible with the caches found in modern processors.Despite of this, multiversioning can cause a series of problems like cache-memory and inter-cache traffic increasing. Moreover, since we need more space on caches, the miss rate may increase as well. Finally, the efficiency of the proposed mechanism must me verified. This efficiency includes not only the overhead that comes from the extra actions the architecture must perform but also the number of squashes that an application, parallelized by a DOPIPE technique, will suffer when executing in our architecture. To evaluate these potential drawbacks, the architecture will be implemented in SESC, a cycle accurate architectural simulator. In addition, the proposed architecture will be expanded in order to support the execution of code parallelized by other techniques.