Combining data and computation transformations for Fine-grain reconfigurable architectures

• Grant number: 12/21068-0
• Support Opportunities: Scholarships abroad - Research Internship - Doctorate
• Start date until: March 04, 2013
• End date until: March 03, 2014
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Eduardo Marques
• Grantee: Cristiano Bacelar de Oliveira
• Supervisor: João Manuel Paiva Cardoso
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
• Institution abroad: Universidade do Porto (UP), Portugal
• Associated to the scholarship: 11/11040-8 - Combining data and computation transformations for Fine-grain reconfigurable architectures, BP.DR

Abstract

The project entitled Combining Transformations and Computation Data for Reconfigurable Architectures for Fine Grain aims to research and develop techniques to generate optimized code, considering issues like memory mapping and memory access for reconfigurable architectures, since the latency treading and writing data has been a bottleneck for high performance applications. These techniques will be employed for developing a compiler for reconfigurable hardware generation from high-level code. Considering the needs for high performance computing systems, to implement algorithms directly into hardware by using FPGAs (Field-programmable Gate Arrays) is an alternative that produces good results. However, to programming FPGAs efficiently is a difficult task. This fact limits the number of FPGA developers, once the common programmers are used to traditional sequential programming paradigm. Thus, we seek to develop mechanisms to facilitate hardware development with FPGAs, by memory usage optimization and by exploiting the parallelism of operations. According to this focus, this work uses the LALP language for implementation of the proposed compiler. By using LALP is expected to allow both memory usage and loop control optimizations. The LALP language was developed in the Reconfigurable Computing Laboratory of the Institute of Mathematical and Computer Sciences, University of São Paulo, in partnership with the Faculty of Engineering of University of Porto, in Portugal. Once LALP still holds some limitations, this research intends to expand its functionalities, by creating a LALP expansion that incorporates mechanisms to address such issues. Then, it is expected to facilitate the implementation of projects and products related to high performance computing that involves reconfigurable architectures. (AU)