Design space exploration on heterogeneous systems for high performance applications

• Grant number: 16/13327-6
• Support Opportunities: Scholarships abroad - Research Internship - Doctorate (Direct)
• Effective date (Start): November 15, 2016
• Effective date (End): November 14, 2017
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Vanderlei Bonato
• Grantee: Leandro de Souza Rosa
• Supervisor: Christos-Savvas Bouganis
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
• Research place: Imperial College London, England
• Associated to the scholarship: 14/14918-2 - Code snippets identification for pipeline processing in FPGA accelerators for heterogeneous platforms, BP.DD

Abstract

Hardware design space exploration is known as a complex field of study, since application can be implemented in different ways, varying in hardware resources, energy consumption and throughput. This problem becomes even more complex when we consider a reconfigurable hardware based on FPGA to create accelerators from application snippets, where we have a design space exploration nested in another one, since the whole application becomes also part of the problem. A solution to avoid the time consuming synthesis during design space exploration is to have a model for the hardware implementation based on the source code, being it an RTL, an OpenCL or a C code. The proposed models in the literature aim different aspects of a hardware design, as the resources modeling, bandwidth constraints, communication costs or power consumption. Furthermore, some models are proposed for a pure FPGA design, while few target host-accelerator architecture. In this project we propose the creation of a model to estimate the hardware metrics of an OpenCL accelerator kernel based on its C code. As result, we expect a model that captures the important aspects of the C language for the hardware generation as an estimation of the input data volume, computation/data rate, and throughput, and also we expect an estimation of the hardware resources of the given kernel. In a second part of this project, we propose to expand the model to estimate the effects of loop transformation techniques on the design metrics, what will help to decide which transformations should be applied to the kernel snippet in order to achieve a better accelerator. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

ROSA, LEANDRO DE SOUZA; BOUGANIS, CHRISTOS-SAVVAS; BONATO, VANDERLEI. Scaling Up Modulo Scheduling for High-Level Synthesis. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v. 38, n. 5, p. 912-925, MAY 2019. (16/13327-6)