High-level mapping framework for heterogeneous architectures with FPGAs and GPUs

• Grant number: 18/22289-6
• Support Opportunities: Scholarships abroad - Research Internship - Doctorate (Direct)
• Start date: January 01, 2019
• End date: December 31, 2019
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Vanderlei Bonato
• Grantee: Andre Bannwart Perina
• Supervisor: Juergen Becker
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
• Institution abroad: Karlsruhe Institute of Technology (KIT), Germany
• Associated to the scholarship: 16/18937-7 - Energy-aware design space exploration framework for heterogeneous architectures with FPGAs and GPUs, BP.DD

Abstract

To increase computing performance while keeping energy consumption to an acceptable budget, heterogeneous systems are currently investigated. By using dedicated compute units as accelerators to speedup specific parts of an application, hardware resources are better utilized resulting in a more energy efficient computing system. However, the task of performing such application mapping to accelerators is still a challenge, requiring knowledge beyond software domain in order to understand which part of the code fits better to the capability of the hardware available. Currently, there are tools supporting unified front ends and languages to simplify the programming of such heterogeneous systems, however there is still a high dependency of the user to manually perform the final mapping process. This work proposes to infer the most suitable regions of a high-level code to be mapped on FPGA or GPU through performance and power estimation. Furthermore, design space exploration is proposed for further performance optimization, all performed without the need of time-consuming synthesis for FPGA. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

PERINA, ANDRE B.; SILITONGA, ARTHUR; BECKER, JURGEN; BONATO, VANDERLEI. ast Resource and Timing Aware Design Optimisation for High-Level Synthesi. IEEE TRANSACTIONS ON COMPUTERS, v. 70, n. 12, p. 2070-2082, DEC 1 2021. (18/22289-6, 16/18937-7)

PERINA, ANDRE BANNWART; BECKER, JUERGEN; BONATO, VANDERLEI; IEEE. Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. 2019 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2019), v. N/A, p. 4-pg., 2019-01-01. (18/22289-6)

PERINA, ANDRE BANNWART; BECKER, JUERGEN; BONATO, VANDERLEI; IEEE. ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. 2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), v. N/A, p. 4-pg., 2019-01-01. (18/22289-6, 16/18937-7)