Custom heterogeneous hardware acceleration for high-performance computing applications

• Grant number: 13/08157-6
• Support type: Research Grants - Visiting Researcher Grant - International
• Duration: November 01, 2013 - November 09, 2013
• Field of knowledge: Physical Sciences and Mathematics - Computer Science
• Principal Investigator: Eduardo Marques
• Grantee: Eduardo Marques
• Visiting researcher: Pedro Nuno Cruz Diniz
• Visiting researcher institution: University of Southern California (USC), United States
• Home Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil

Abstract

High-Performance Computing (HPC) is at the core of many scientific and engineering challenges with tremendous impact in our modern-day life needs. Understanding the causes and predicting and potential impacts of climate change in our natural resources, agricultural productions; improving the efficiency of combustion or developing real-time strategies for physical resource allocation in the presence of network failures as well as a variety of national security challenges, requires sustained high-performance computing computational capabilities. While the HPC needs and industrial and academic communities have developed large-scale machines capable of impressive sustained concurrent computations with aggregate Peta-flops calculations rates, the increasing demand for computing power through technological improvements such as lithographical techniques and increase clock rates have substantially slowed down due to energy and resilient issues. The base cores of these machines exhibit fairly low computational efficiencies and further performance and energy gains are slim at best. The tack to highly concurrent machines increases not only the energy requirements for these large-scale machines but also exacerbate the difficulty in effectively programing them. As a result both performance and programmers are highly non-portable. An architectural approach that addresses these concerns of power efficiency and high-performance capabilities relies on the use of Field-Programmable Gate-Arrays (FPGAs) or Graphics Processor Units (GPUs) as hardware accelerator units as depicted in figure 1. In this architectural organization the FPGAs/GPUs act as co-processors or a traditional processor units and carry out specific computations for which they can be custom-programmed to be extremely powerful and computing efficient. Their flexibility thus allows them to achieve orders of magnitude better performance than conventional computing systems via customization. In terms of the overall system-level programming this "master-slave" model is very intuitive to grasp and can be easily implemented as part of the back-end of a traditional compiler. (AU)