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Using genetic algorithms for the automatic generation of configurable architectures for the optimization of c code instructions

Grant number: 10/19285-7
Support type:Research Grants - Visiting Researcher Grant - International
Duration: April 28, 2011 - May 11, 2011
Field of knowledge:Physical Sciences and Mathematics - Computer Science
Principal Investigator:Eduardo Marques
Grantee:Eduardo Marques
Visiting researcher: Pedro Nuno Cruz Diniz
Visiting researcher institution: University of Southern California (USC), United States
Home Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil


This project aims at the automatic generation of configurable and application-specific custom FPGA-based architectures starting from the analysis of various sample kernel C codes. Previous research in this area has identified several performance advantages and power-savings opportunities over non-optimized or non-customized architectures. Unfortunately, the lack of tools that explore the various architectural trade-offs in an automated fashion has effectively hampered the development of good custom FPGA-based architectures. In this context we propose a research project to develop and validate the use of genetic algorithm techniques in this automated design-space exploration of configurable low-power and still high-performance architectures. We will investigate the use of genetic algorithms in findings good solutions to specific architectural problems as these algorithmic techniques have proved to be very effective in the context of Place-and-Route to find solutions to equally complex problems. To guide the application of these algorithms we expect to develop specific genetic operator (such as cross-over and mutation operators) that are specific to this architecture optimization domain and that have into account the structure of high-level instructions in selected C kernel codes. As part of our success evaluation strategy, we will simulate the performance of the generated architectures comparing them in terms of power and wall-clock time against the execution on more traditional configurable computing cores such as an PowerPC macro core executing on an FPGA. (AU)