Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation

Autor(es)

Salamanca, Juan ^[1] ; Amaral, Jose Nelson ^[2] ; Araujo, Guido ^[1]

Afiliação do(s) autor(es)

^[1] Univ Estadual Campinas, Inst Comp, BR-13083852 Sao Paulo - Brazil

^[2] Univ Alberta, Dept Comp Sci, Edmonton, AB T6G 2R3 - Canada

• Tipo de documento: Artigo Científico
• Fonte: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS; v. 29, n. 2, p. 466-480, FEB 2018.
• Citações Web of Science: 2

Resumo

This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS) and describes a careful evaluation of the implementation of TLS on the HTM extensions available in such machines. The sample implementation of TLS over HTM described in this paper also provides evidence that the programming effort to implement TLS over HTM support is non-trivial. Thus the paper also describes an extension to OpenMP that both makes TLS more accessible to OpenMP programmers and allows for the easy tuning of TLS parameters. As a result, it provides evidence to support several important claims about the performance of TLS over HTM in the Intel Core and the IBM POWER8 architectures. Experimental results reveal that by implementing TLS on top of HTM, speed-ups of up to 3.8 x can be obtained for some loops. (AU)

• Processo FAPESP: 13/08293-7 - CECC - Centro de Engenharia e Ciências Computacionais
• Beneficiário: Munir Salomao Skaf
• Modalidade de apoio: Auxílio à Pesquisa - Centros de Pesquisa, Inovação e Difusão - CEPIDs
• Processo FAPESP: 15/12077-3 - Execução especulativa de código em arquiteturas multicore
• Beneficiário: Juan Jesús Salamanca Guillén
• Modalidade de apoio: Bolsas no Exterior - Estágio de Pesquisa - Doutorado Direto