| Full text | |
| Author(s): |
Total Authors: 3
|
| Affiliation: | [1] Univ Estadual Campinas, Inst Comp, BR-13083852 Sao Paulo - Brazil
[2] Univ Alberta, Dept Comp Sci, Edmonton, AB T6G 2R3 - Canada
Total Affiliations: 2
|
| Document type: | Journal article |
| Source: | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS; v. 29, n. 2, p. 466-480, FEB 2018. |
| Web of Science Citations: | 2 |
| Abstract | |
This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS) and describes a careful evaluation of the implementation of TLS on the HTM extensions available in such machines. The sample implementation of TLS over HTM described in this paper also provides evidence that the programming effort to implement TLS over HTM support is non-trivial. Thus the paper also describes an extension to OpenMP that both makes TLS more accessible to OpenMP programmers and allows for the easy tuning of TLS parameters. As a result, it provides evidence to support several important claims about the performance of TLS over HTM in the Intel Core and the IBM POWER8 architectures. Experimental results reveal that by implementing TLS on top of HTM, speed-ups of up to 3.8 x can be obtained for some loops. (AU) | |
| FAPESP's process: | 13/08293-7 - CCES - Center for Computational Engineering and Sciences |
| Grantee: | Munir Salomao Skaf |
| Support Opportunities: | Research Grants - Research, Innovation and Dissemination Centers - RIDC |
| FAPESP's process: | 15/12077-3 - Speculative code execution for multicore architectures |
| Grantee: | Juan Jesús Salamanca Guillén |
| Support Opportunities: | Scholarships abroad - Research Internship - Doctorate (Direct) |