Non-iterative SDC modulo scheduling for high-level synthesis

Autor(es)

Rosa, Leandro de Souza ^[1] ; Bouganis, Christos-Savvas ^[2] ; Bonato, Vanderlei ^[1]

Afiliação do(s) autor(es)

^[1] Univ Sao Paulo, Inst Math & Comp Sci, Av Trabalhador Sao Carlense 400, Sao Carlos - Brazil

^[2] Imperial Coll London, Dept Elect & Elect Engn, Exhibit Rd, London SW7 2BU - England

• Tipo de documento: Artigo Científico
• Fonte: MICROPROCESSORS AND MICROSYSTEMS; v. 86, OCT 2021.
• Citações Web of Science: 0

Resumo

High-level synthesis is a powerful tool for increasing productivity in digital hardware design. However, as digital systems become larger and more complex, designers have to consider an increased number of optimizations and directives offered by high-level synthesis tools to control the hardware generation process. One of the most explored optimizations is loop pipelining due to its impact on hardware throughput and resources. Nevertheless, the modulo scheduling algorithms used at resource-constrained loop pipelining are computationally expensive, and their application through the whole design space is often non-viable. Current state-of-the-art approaches rely on solving multiple optimization problems in polynomial time, or on solving one optimization problem in exponential time. This work proposes a novel data-flow-based approach, where exactly two optimization problems of polynomial time complexity are solved, leading to significant reductions on computation time for generating a single loop pipeline. Results indicate that, even for complex loops, the proposed method generates high-quality designs, comparable to the ones produced by existing state-of-the-art methods, achieving a reduction on the design-space exploration time by 2.46x (geomean). (AU)

• Processo FAPESP: 14/14918-2 - Identificação de trechos de código para processamento pipeline em aceleradores FPGA para plataformas heterogêneas
• Beneficiário: Leandro de Souza Rosa
• Modalidade de apoio: Bolsas no Brasil - Doutorado Direto