Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

Autor(es)

Rodrigues, Jaime C. ; Mariniello, Genaro ; Casse, Mikael ; Barraud, Sylvain ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo A. ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 35TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO2021); v. N/A, p. 4-pg., 2021-01-01.

Resumo

This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. (AU)

• Processo FAPESP: 19/15500-5 - Simulação atomística das propriedades elétricas de nanofios transistores MOS
• Beneficiário: Marcelo Antonio Pavanello
• Modalidade de apoio: Auxílio à Pesquisa - Regular