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Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires

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Autor(es):
Paz, Bruna Cardoso ; Pavanello, Marcelo Antonio ; Casse, Mikael ; Barraud, Sylvain ; Reimbold, Gilles ; Vinet, Maud ; Faynot, Olivier ; Sarafis, P ; Nassiopoulou, AG
Número total de Autores: 9
Tipo de documento: Artigo Científico
Fonte: 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017); v. N/A, p. 4-pg., 2017-01-01.
Resumo

This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (W-FIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution. (AU)

Processo FAPESP: 15/10491-7 - Caracterização elétrica e simulação tridimensional de nanofios transistores MOS
Beneficiário:Bruna Cardoso Paz
Modalidade de apoio: Bolsas no Brasil - Doutorado
Processo FAPESP: 16/06301-0 - Caracterização elétrica e simulação tridimensional de nanofios transistores MOS
Beneficiário:Bruna Cardoso Paz
Modalidade de apoio: Bolsas no Exterior - Estágio de Pesquisa - Doutorado