New method for individual electrical characterization of stacked SOI nanowire MOSFETs

Autor(es)

Paz, Bruna Cardoso ; Casse, Mikael ; Barraud, Sylvain ; Reimbold, Gilles ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo Antonio ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2017-01-01.

Resumo

A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (V-B) and consists of three basic main steps, accounting for V-B influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Omega-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150 degrees C. (AU)

• Processo FAPESP: 15/10491-7 - Caracterização elétrica e simulação tridimensional de nanofios transistores MOS
• Beneficiário: Bruna Cardoso Paz
• Modalidade de apoio: Bolsas no Brasil - Doutorado
• Processo FAPESP: 16/06301-0 - Caracterização elétrica e simulação tridimensional de nanofios transistores MOS
• Beneficiário: Bruna Cardoso Paz
• Modalidade de apoio: Bolsas no Exterior - Estágio de Pesquisa - Doutorado