| Texto completo | |
| Autor(es): |
Bergamaschi, F. E.
;
Pavanello, M. A.
;
IEEE
Número total de Autores: 3
|
| Tipo de documento: | Artigo Científico |
| Fonte: | 2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC); v. N/A, p. 4-pg., 2021-01-01. |
| Resumo | |
In this work, the effects of substrate biasing on the electrical behavior of n-type O-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width are analyzed. The analysis is carried over through 3D TCAD simulations calibrated with experimental data. Mobility degradation is observed for negative back bias due to surface-related scattering mechanisms on the front gate channel, while mobility increase is verified for positive back bias values that induce conduction in both front and back channels. High back bias values, however, which activate the back channel prior to the front one, lead to degradation in carrier mobility. On-state-off-state current ratio reduces for positive back bias due to degradation in the subthreshold slope, while DIBL is worsened due to the reduced front gate control when the substrate's positive electric field takes ahold of the inversion charges. (AU) | |
| Processo FAPESP: | 19/15500-5 - Simulação atomística das propriedades elétricas de nanofios transistores MOS |
| Beneficiário: | Marcelo Antonio Pavanello |
| Modalidade de apoio: | Auxílio à Pesquisa - Regular |