| Texto completo | |
| Autor(es): |
Cavallari, Marco R.
[1]
;
Zanchin, Vinicius R.
[2]
;
Valle, Marcio A.
[1]
;
Izquierdo, Jose. E.
[3]
;
Rodriguez, Eduardo M.
[4]
;
Rodriguez, Estrella F. G.
[4]
;
Pereira-da-Silva, Marcelo A.
[5]
;
Fonseca, Fernando J.
[1]
Número total de Autores: 8
|
| Afiliação do(s) autor(es): | [1] Univ Sao Paulo, Escola Politecn, Dept Engn Sistemas Eletron, BR-05424970 Sao Paulo, SP - Brazil
[2] Univ Sao Paulo EPUSP, Polytech Sch, BR-05508010 Sao Paulo, SP - Brazil
[3] Inst Super Politecn Jose Antonio Echeverria, Ctr Invest Microelect, Havana 10800 - Cuba
[4] Inst Super Politecn Jose Antonio Echeverria, Havana 10800 - Cuba
[5] Univ Sao Paulo, Inst Fis Sao Carlos, BR-13566590 Sao Carlos, SP - Brazil
Número total de Afiliações: 5
|
| Tipo de documento: | Artigo Científico |
| Fonte: | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY; v. 15, n. 3, p. 342-351, SEP 2015. |
| Citações Web of Science: | 2 |
| Resumo | |
Polymeric transistor degradation was investigated on bottomand top gate structures. Shelf-lifetime studies in both kinds of devices demonstrate an accelerated increase in effective charge carrier mobility, threshold voltage, and off current in modulus when poly(3-hexylthiophene) (P3HT) is exposed to atmospheric gases. Although P3HT is underneath PMMA dielectric and gold gate electrode films, electrical parameters degradation can be only delayed by 100 h. Therefore, only glass encapsulation of the active area is capable of effectively preventing current modulation decrease after exposure to atmospheric gases. Differently from their bottom-gate counterparts, capped top-gate TFTs clearly present negative threshold voltage and positive hysteresis. An interface with reduced deep traps concentration and electrical characterization influence on shallow traps filling are believed to play a significant role in these top-gate P3HT/PMMA transistors under operating conditions. Alternating gate voltage stress along 3000 cycles provides evidence of electrical sweep as a cause of performance degradation. Similarly, dc gate bias stress monitored for 127 min can impair current modulation and shifts threshold voltage depending on its sign. Finally, reversibility of both kinds of stress points that shallow traps are the major problem in these capped devices. (AU) | |
| Processo FAPESP: | 08/57706-4 - Instituto Nacional de Eletrônica Orgânica (INEO) |
| Beneficiário: | Roberto Mendonça Faria |
| Modalidade de apoio: | Auxílio à Pesquisa - Temático |
| Processo FAPESP: | 13/19420-0 - Sensores de gás a base de transistores de filmes finos orgânicos |
| Beneficiário: | Marco Roberto Cavallari |
| Modalidade de apoio: | Bolsas no Brasil - Pós-Doutorado |
| Processo FAPESP: | 09/05589-7 - Estudo e desenvolvimento de LEDs orgânicos, células solares, transistores de filmes finos e sensores baseados em polímeros semicondutores |
| Beneficiário: | Adnei Melges de Andrade |
| Modalidade de apoio: | Auxílio à Pesquisa - Regular |